In today's rapidly advancing semiconductor manufacturing industry, through-silicon vias, (TSVs), are key elements in integrated circuit packaging technology. TSVs are vias that extend completely through the semiconductor substrate, commonly a silicon wafer, to allow chip-to-chip interconnect schemes or wafer-to-wafer interconnect schemes compatible with 3D wafer-level packaging. The TSVs are filled with conductive material, and connective pads or other structures are formed on top and bottom of the conductive material, i.e. on the upper and lower opposed surfaces on the semiconductor substrate. This arrangement enables individual die to be stacked over one another and coupled to one another or other components, without the use of wire bonding.
The conductive material extending through and filling the TSV is conventionally surrounded by a dielectric layer which serves to isolate the filled TSV from the substrate. The dimensions of the TSVs that extend completely through the substrates are great compared to the interconnect features of the semiconductor device such as the vias formed within the semiconductor devices and which connect the different levels of metallization to one another through dielectric material within the semiconductor devices. As a result of the enormous size of the TSV, the parasitic capacitance created in the dielectric layer surrounding the TSV is significant and creates vulnerability to substrate noise.
Conventional attempts to correct for or compensate for the large parasitic capacitance have typically required extra shielding which, in turn, requires additional masking operations and this significantly lowers throughput and increases costs. The present disclosure is directed to addressing these shortcomings and reducing parasitic capacitance.